The conventional DRAM memory cells for storing information have stack capacitors or trench capacitor. In the case of a stack capacitor, a high stack structure has to be built in a narrower space in order to obtain a capacitance sufficient for a high density device, with the result that the step coverage is not smooth. Meanwhile, in the case of trench capacitor, the isolation between trenches becomes insufficient, and the manufacturing process are complicated.
The method for fabrication of a conventional stack capacitor cell will be briefly described below.
As shown in FIG. 1A, first a MOS transistor fabrication process is carried out by forming a field oxide 2 for isolating active regions, a gate electrode 3 and a source/drain region 4 upon a semiconductor substrate 1, and then, an insulating layer 5 is formed thereupon.
Then a polysilicon 6 is deposited over entire wafer so as for it to serve as a lower electrode of the stack capacitor, and then, a buried contact hole is formed by applying a process of photolithography (photo-etching process) using a photoresist 7, as shown in the FIG. 1B.
Then the photoresist 7 is removed, and a polysilicon 8 is deposited to serve as a lower node (storage electrode) of the stack capacitor. Then a contact 10 is formed, and a lower storage node of a stack capacitor is patterned by applying a photolithography and etching process using a photoresist 9, as shown in the FIG. 1C.
Then The photoresist is removed, a high dielectric material 11 (O-N-O, N-O or the like) is coated, a polysilicon is deposited over entire wafer, and a plate electrode 12 (upper electrode) of the stack capacitor is formed.
In the conventional technique as described above, the capacitance of the stack capacitor is not sufficient for a high density DRAM cell (e.g., 64M). Meanwhile, in the case where a fin structure or a cylindrical structure is adopted in order to increase the capacitance, the step coverage becomes worse, thereby inviting difficulty in carrying out the next step.